This checks to make sure that the DMA engine is initialized properly and that packets can travel through the device. It will only work in DMA mode, not PIO.
Note, I'm not sure if the uCode has to be uploaded first, but I'd suspect that you would have to
- Perform an ("80211CoreReset") on all cores (Note, the device should be down by now)
Turn the PowerControl crystal back on
- If we're in DMA mode, initialize the DMA TX channel and the DMA RX channel. If we're in PIO mode, write 0x100 (Direct FIFO RX mode) to the first DMA recieve channel control word.
- Enable FIFO Loopback mode by setting bit 0x4 in the first DMA transmit channel control word. (For both PIO and DMA)
- Create a packet to send with the data below
- Send the packet
For DMA, lock the DMA workaround semaphore and if it's not 0, return, otherwise, we set the PowerSavingControlBits bit 26 and compute bit 25, then send the packet as is
- For PIO, we just write out the packet as is
- Loop 100 times or until the saved first DMA Channel IRQ Reason register has any of bits 0xFD00 set
- Delay 10 uSec
- Get the first DMA Channel IRQ Reason register and perform the PIO Interrupt Workaround if needed
- Save the possibly patched DMA Channel IRQ Reason register value for checking in the loop
- Loop 500 times or until we recieve a packet
- Check the queues for a recieved packet
- Delay 10 uSec
- If we recieved a packet
- Compare the 0x20 bytes of data in the packet sent with the data in the packet recieved (Note that because of the RX Header in the recieved packet, you must start your comparison at offset 0x1E for PIO mode or offset 0x1A for DMA mode), the test is a success if the packets match
- If we're in DMA mode, reset and reclaim the DMA TX channels and descriptors
This is given in 32 bit chunks for convenience. I don't think the data is significant, it just looks like it's testing different bit combinations.
0x00000000, 0xFFFFFFFF, 0x55555555, 0xAAAAAAAA, 0x33333333, 0xCCCCCCCC, 0x66666666, 0x99999999