Init

The following operations are done on the chipcommon core. If it is not present, no initialisation is necessary. Afterwards, you should switch back to the previously selected core.

1. If the ChipCommon Chip ID is 0x4321 and the Chip Revision is 1

   1. Write 0x00A4 to the ChipCommon Core Chip Control register (0x28)

2. If the ChipCommon Chip ID is 0x4321 and the Chip Revision is 0

   1. Write 0x03A4 to the ChipCommon core Chip Control register (0x28)

3. Check if the ChipCommon Core Capabilities field has the Power Control bit set (0x40000) and if not, abort

4. If the ChipCommon Core reivsion is 10 or higher

   1. MaskSet the ChipCommon Instaclock System Clock Control register with mask 0x0000FFFF and set with 0x40000 (Sets the Idle Low Power clock rate to 1MHz)

5. Otherwise
   1. Find the maximum slowclock frequency (see below)
   2. Set pll_on_delay to (maxslowfreq * 150 + 999999) / 1000000
   3. Set fref_sel_delay to (maxslowfreq * 15 + 999999) / 1000000

Get Fast Powerup Delay

1. Set the return value to 0 if the chipset isn't on PCI, has no chipcommon core or no powercontrol capabilities
2. Get the min slowclock frequency and the chipcommon's pll_on_delay register value
3. Return (((pll_on_delay + 2) * 1000000) + (minslowclockfreq - 1)) / minslowclockfreq

PowerControl Crystal

Note that the PCI-E Core doesn't have the ability to control the Crystal Powerup, these instructions are only for the PCI Core

Turning the Crystal On

1. Read from PCI Register 0xB0 (GPIO In Register). If bit 0x40 (Crystal Powerup) is set, the Crystal is already on and we return.
2. Set bits 0x80 (PLL Powerdown) and 0x40 (Crystal Powerup) in PCI Register 0xB4 (The GPIO Out Register)
3. Set bits 0x80 (PLL Powerdown) and 0x40 (Crystal Powerup) in PCI Register 0xB8 (The GPIO Enable Register)
4. Delay for 1000 uSecs
5. Unset bit 0x80 (PLL Powerdown) in PCI Register 0xB4 (The GPIO Out Register)
6. Delay for 5000 uSecs

Turning the Crystal Off

1. If radio is hardware-disabled, the Core Revision is < 5 or the BoardFlags have BFL_XTAL set, return, we don't do anything

2. Set the PowerControl clock to slow

3. Set bit 0x80 (PLL Powerdown) and unset bit 0x40 (Crystal Powerup) in PCI Register 0xB4 (The GPIO Out Register)
4. Set bits 0x80 (PLL Powerdown) and 0x40 (Crystal Powerup) in PCI Register 0xB8 (The GPIO Enable Register)

PowerControl Set Clock

Three clock modes are possible: Slow, Fast and Dynamic

1. If the core revision of the ChipCommon core is < 6 turn do a PowerControl Set Crystal On if the desired mode is fast, otherwise, do nothing

2. If the core revision of the ChipCommon core is >= 10 the clock can't be set, return

3. Ensure that this ChipCommon Core has PowerControl capabilities

4. If the COREREV is >= 6, depending on mode:

   Fast

   Unset bit 0x800 (Force Slow) and bit 0x2000 (Dynamic Crystal) and set bit 0x1000 (Force PLL) in the slow_clk_ctl register

   Slow

   Set bit 0x800 (Force Slow) in the slow_clk_ctl register

   Dynamic

   Unset bit 0x800 (Force Slow) and bit 0x1000 (Force PLL) and set bit 0x2000 (Dynamic Crystal) in the slow_clk_ctl register

Slow Clock

Slow Clock Sources

There are three possible sources for the Slow Clock to find which to use:

1. If the ChipCommon core revision is less than 6

   1. If this is a PCMCIA bus, we're using the on chip Crystal Slow Clock oscillator
   2. If this is a PCI bus, read the value of the PCI Configuration space register 0xB4 (PCI GPIO Out). If bit 4 (0x10) is set, we're using the PCI Clock, otherwise, we're using the Crystal Slow Clock oscillator
   3. If we're using a Silicon backplane bus, we're using the Crystal Slow Clock oscillator

2. If the ChipCommon core revision is less than 10

   1. Read the contents of the Slow Clock Control register in the ChipCommon core and mask with 0x7. If the value is 0, we're using the on chip Low Power oscillator. If the value is 1, we're using the Crystal Slow Clock oscillator. If the value is 2, we're using the external PCI clock.

3. Otherwise, we're using the Crystal Slow Clock oscillator

Finding the Slow Clock Frequencies

1. Make sure that the chipcommon core is set and that it has PowerControl capabilities

2. Find the Slow Clock source

3. If the Core Revision of the ChipCommon core is < 6

   1. If the source is the PCI clock, the divisor is 64
   2. If the source is the Crystal Slow clock oscillator, the divisor is 32

4. If the Core Revision of the ChipCommon core is > 6 and < 10

   1. If the source is the Low Power oscillator, set the divisor to 1

   2. If the source is the Crystal Slow clock oscillator or the PCI clock, find the divisor by reading the Slow Clock Control register from the ChipCommon core, bitwise AND that with 0xFFFF0000, then shift right by 16. Add one to the result and then multiply that by 4.

5. If the ChipCommon core is >= 10

   1. Read the value of the System Clock Control register in the ChipCommon core and shift that value right by 16. Add one to the result and then multiply that by 4.

6. Find the frequency value in the table below and find the maximum and minimum values by dividing that value by the devisor