Initializes the 802.11 core

1. If the backplane has a PCI Core (not PCI-E) with revision 5 or less
   1. Unset bits 0x70 (Request Timeout Mask) and 0x7 (Service Timeout Mask) and set bits 0x32 in sbmiconfiglow

2. PHYCalibration

3. ChipInit

4. BSInit

5. Write 0 to SHM offset 0x16 (16 bits)

6. Save the value of SHM offset 0x5E

7. If (In our version of the driver, always false, not sure what it's for)

   1. Set bit 0x10 in the saved value of SHM offset 0x5E

8. If this is a B or G PHY

   1. Set bit 0x2 in the saved value of SHM offset 0x5E

9. If this is a G PHY with PHY Revision 1

   1. Set bit 0x20 in the saved value of SHM offset 0x5E

10. If this is a B PHY with PHY Revision >= 2 and Radio ID 0x2050

    1. Unset bit 0x20 in the saved value of SHM offset 0x5E

11. If this is a G PHY and the BoardFlags BFL_PACTRL are set

    1. Set bit 0x40 in the saved value of SHM offset 0x5E

12. If the saved value of SHM offset 0x5E isn't the same as what's currently in 0x5E

    1. Write the saved value of SHM offset 0x5E back into SHM offset 0x5E

13. If the 802.11 Core Revision is >= 5

    1. Write 0xC to MMIO offset 0x43C

14. If we're not in PIO mode

    1. Initialize the 4 TX DMA channels

    2. Initialize the first RX DMA channel

    3. If this Core Revision is < 5

       1. Initialize the 4th RX DMA channel

    4. Figure out how many buffers we need in the initialized RX DMA channels, then allocate, initialize and add them.

15. Write 0x50 to the 16-bit register 0x612
16. Write 0x50 to SHM offset 0x416, 0x1F4 to SHM offset 0x414

17. EnableMAC

18. Enable the Interrupts by writing the General Interrupt Mask to MMIO offset 0x128