Contents
Accessing Radio Registers
The PHY Radio Registers are accessed through the MMIO at memory locations 0x3F6 (offset) and 0x3F8(value high 16 bits) 0x3FA (value low 16 bits).
It appears that G PHYs have 128 registers, offsets (0x0 - 0x7F), values above that seem to loop back, excluding the special offset of 0x1.
Writing to a Radio Register
To write to a radio register:
Write the 16 bit offset of the desired Radio Register to MMIO address 0x3F6
Write the 16 bit value to be written to the Radio Register to MMIO address 0x3FA
Reading From a Radio Register
When reading from a radio register, there are differences for various PHYs:
Note: for all PHY versions, if the offset is 1, do not adjust the offset.
PHY Version |
Offset Adjust |
A PHYs |
offset |= 0x40 |
B PHYs |
Check (RadioID & 0x0FFFF000) for the B PHY version |
0x02053000 |
If the offset < 0x70, offset +=0x80 |
0x02053000 |
If the offset < 0x80, offset +=0x70 |
0x02050000 |
offset |= 0x80 |
G PHYs |
offset |= 0x80 |
Once the offset is calculated:
Write the 16 bit offset of the desired Radio Register to MMIO address 0x3F6
Read the 16 bit value retrieved from the Radio Register by reading from MMIO address 0x3FA
The only place where a 32 bit value is read is when the offset is 0x01. This offset contains the RadioID. To retrieve this value, the offset 0x01 is written to 0x3F6 for each 16 bit read, first the high part of the value (from 0x3F8) and then the lower value (from 0x3FA).
Table of Radio Register Offsets and Functionality
Radio Register Offset |
Size (bits) |
Functionality |
0x01 |
32 |
|
0x04 |
16 |
Probably a bit field. Set to 0xC0 when turning on a 2060 radio and set to 0xFF when turning off a 2060 radio. The value of PHYRegister 0x5A also seems to be related. (A PHY Only) |
0x05 |
16 |
Used in 2060RadioInit |
0x06 |
16 |
Used in 2060RadioInit |
0x09 |
16 |
|
0x15 |
16 |
|
0x17 |
16 |
|
0x19 |
16 |
|
0x1E |
16 |
Result of LOF Cal |
0x2C |
16 |
|
0x32 |
16 |
|
0x34 |
16 |
|
0x3F |
16 |
|
0x43 |
16 |
Radio Attenuation Level also TX CTL Register for 0x2050 Radios with Radio Rev 8 |
0x50 |
16 |
|
0x51 |
16 |
|
0x52 |
16 |
TX CTL Register, outlined below |
0x53 |
16 |
|
0x54 |
16 |
|
0x5A |
16 |
|
0x5B |
16 |
|
0x5C |
16 |
|
0x5D |
16 |
|
0x5E |
16 |
|
0x60 |
16 |
Baseband Attenuation (see AttenuationControl) |
0x75 |
16 |
|
0x76 |
16 |
TX Path Power, bits 2 and 7 are set on if TX Path Power is on (2050 Radios only) |
0x78 |
16 |
Seems only bits 1 - 4 are used, on GPHYs, the result from 2050RadioCoreCalibration is stored here. |
0x79 |
16 |
|
0x7A |
16 |
|
0x7D |
16 |
|
0x80 |
16 |
|
0x81 |
16 |
|
0x82 |
16 |
|
0x85 |
16 |
|
Register 0x52
Bits |
||
31 - 7 |
6 -4 |
3 - 0 |
Probably Unused |
TX CTL1 Attenuation Value (2050 radios only) |
TX CTL2 Attenuation Value (1st LO Measure Loop) |