Contents
Interrupts On
To turn on the interrupts, the saved interrupt mask is written to MMIO 0x12C.
Interrupts Off
To turn off the interrupts, save the current interrupt mask from MMIO 0x12C and write 0 to the interrupt mask register.
Handling Interrupts
When the ISR is called, the value of MMIO offset 0x128 is read. If this value is 0xFFFFFFFF, then the interrupt was not meant for this card. If the interrupt was meant for this card, we retrieve the interrupt mask from MMIO offset 0x12C. If the bitwise AND of the interrupt and the mask is 0, we can ignore the interrupt, otherwise, we write the AND'ed value back to MMIO register 0x128 (This appears to acknowledge the IRQ). In addition to 0x128, the DMA/PIO reasons need to be read and masked in the same manner as the Generic Interrupt Reason register. The offsets and masks follow below:
DMA/PIO Interrupt Register |
Mask |
0x20 |
0x1DC00 |
0x28 |
0xDC00 |
0x30 |
0xDC00 |
0x38 |
0x1DC00 |
If we are in PIO mode and the 802.11 Core Revision is < 3, we need to perform this additional workaround before acknowledging the interrupt. Check if Generic Interrupt Reason 0x100 is set. If so, we make no further changes to the interrupt values. Otherwise, loop over the PIO RX Control Registers of each of the Queues. If the PIO RX Control Register has bit 0 unset, we unset bit 0x10000 of the saved PIO IRQ reason (Mask 0xFFFEFFFF), otherwise, we set that bit.
The saved interrupt values are handed to a tasklet for processing.
Generic Interrupts
The interrupt reason register (0x128 in the MMIO) consists of the following:
Mask |
Usage |
0x00000001 |
Ready |
0x00000002 |
Beacon |
0x00000004 |
PS Interrupt |
0x00000020 |
Reg124 |
0x00000040 |
Power Management Queue |
0x00000100 |
PIO Workaround |
0x00000800 |
Fatal Error |
0x00002000 |
Reset (Error?) |
0x00008000 |
Data Received (or RX DMA Error?) |
0x00010000 |
Scan |
0x00020000 |
RM CCA Interrupt |
0x00040000 |
Noise |
0x01000000 |
BSS CFG Disable |
0x10000000 |
Scan |
0x20000000 |
Transmit Status |
0x80000000 |
Cram Close |
Cram Close
When this interrupt occurs,
Write 0 to MMIO offset 0x18
If we have data that we've been saving to bundle in a Cram packet, send it now
Transmit Status
When this interrupt is set, the retrieve the TransmitStatus. Note that on cores with revision < 5, the last DMA controller or PIO queue can also also get the DMA recieve done interrupt, which also triggers the TransmitStatus retrieval process. The driver should be prepared to deal with both interrupts at any time, on any revision. In AP mode, this interrupt also initiates the sending of powersave responses.
BSS CFG Disable
FIXME
Noise
When this interrupt is set and we're collecting link quality information, the interrupt indicates that the link quality information should be updated. See LinkQuality for more details.
RM CCA Interrupt
Radio Monitoring - Clear Channel Assessment - FIXME describe this
Scan
If we're scanning and the TX DMA/PIO Queue (1) is suspended when this IRQ occurs, we setup a timer. This timer appears to be handling the actual scanning in software. I'm not sure what triggers these IRQs.
Reset (Error?)
Resets the chip in the same manor as a DMA error, probably an error condition
Fatal Error
We got this one while testing things when by accident the template ram wasn't set to big endian when it should have been after writing the initial values. It keeps on being triggered, the only way to stop it seems to shut down the chip.
Power Management Queue
Reg124
When this bit is set and the variable that keeps track of whether to set bit 4 in the Reg124BitField is true, set bit 4 in the Reg124BitField
PS Interrupt
When this interrupt is set, perform the PS Interrupt routine (Note, this must come before taking care of the Reg124 interrupt)
Beacon
On this interrupt, if this is an AP, UpdateBeaconPacket in the TemplateRam. Make sure this interrupt is disabled while updating the beacon packet.
Ready
May be a "ready" indicator, as in it's 0 when busy and 1 when ready. Checked when enabling/disabling the MAC.