The PHY Registers are accessed through the MMIO offsets 0x3FC and 0x3FE. PHY Registers are 16 bits wide.
Reading from PHY Registers
Write the desired 16 bit register offset to MMIO offset 0x3FC
Read the 16 bit value from MMIO offset 0x3FE
Writing to PHY Registers
Write the desired 16 bit register offset to MMIO offset 0x3FC
Write the 16 bit value to MMIO offset 0x3FE
PHY Registers by Offset
Offset |
Usage |
0x8 |
|
0x14 |
|
0x17 |
Bits 0-3 (TX Gain Base Band) Bit 4 (TX Gain TX Mix) Bit 5 (Always Set) |
0x18 |
Used by FrequencyTracking |
0x19 |
Bits 0-2 (TX Gain RF Programmable Gain Amplifier) Bits 3-4 (TX Gain RF PAD) Bits 5-7 (TX Gain Radio Frequency Power Amplifier) |
0x20 |
NRSSI Threshold |
0x26 |
|
0x29 |
Bit 0x8000 is the APY all CRS switch on A PHYs, this is the power control register to save for the B PHY InitPowerControl, this is also the TSSI value returned for BPHYs and the lower 8 bits of the TSSI value for GPHYs |
0x2A |
|
0x2D |
A PHY TX Power? |
0x2E |
LocalOscillator control register mask (B PHYs) |
0x2F |
LocalOscillator control register (B PHYs) |
0x30 |
|
0x32 |
|
0x35 |
|
0x38 |
Used by FrequencyTracking |
0x46 |
|
0x49 |
Only bit 0x200 is used, Afterburner related (APHY) |
0x5A |
Seems to be related to the A PHY Status register? |
0x60 |
B/G PHYs with version >= 1 have the baseband attenuation value here in bits 2-5 (version > 1) or bits 3-6 (version 1) |
0x63 |
RX IQ (A PHY) |
0x69 |
IQ Comp Delta (add TX IQ) (A PHY) |
0x6A |
BB loft cancel (A PHY) |
0x72 |
PHY InternalLookupTable Control (A PHY), probably advances automatically for each write to 0x73 (FIXME: test) |
0x73 |
PHY InternalLookupTable Data (A PHY) |
0x74 |
PHY InternalLookupTable Data (?) (A PHY) |
0x7B |
This is the power control register to save in APHY Init, this is also the TSSI value returned for APHYs |
0x7C |
APHY Temperature sense (bitfield? bit 0 is set) (A PHY) |
0x88 - 0xA7 |
BPHYs - Initialized with values from 0x3C3D to 1 |
0xED |
|
0x3A0 - ? |
GPHY DC Lookup Table |
0x3C0 - 0x3FF |
GPHY Gain Look up Table |
0x401 |
G Radio Bit Field (?) - Known to contain antenna div, bit 11 is the "bad frame preemption" bit |
0x406 |
APHY CRS ED Workaround (PHY Revision 1) |
0x429 |
Bit 0x8000 is the APHY all CRS switch on G PHYs, Bit 0x4000 is used in non-wlan interference mode also used for APHY CRS Threshold Workaround |
0x42B |
APHY CRS ED Workaround (PHY Revision > 1) |
0x42C |
APHY CRS Blank Workaround |
0x449 |
Only bit 0x200 is used, Afterburner related (GPHY) |
0x472 |
PHY InternalLookupTable Control (G PHY), probably advances automatically for each write to 0x473 (FIXME: test) |
0x473 |
PHY InternalLookupTable Data (G PHY) |
0x474 |
PHY InternalLookupTable Data (?) (G PHY) |
0x47B |
Upper 8 bits of GPHY TSSI value |
0x48A |
Lower 12 bits are two 6 bit signed values of the NRSSI Threshold (G PHYs) |
0x4A7 |
APHY CCK Shift Bits Workaround |
0x4C0 |
APHY CRS ED Workaround (PHY Revision > 1) |
0x4C1 |
APHY CRS ED Workaround (PHY Revision > 1) |
0x802 |
GPHY (Classify CTL?) Some sort of bitfield |
0x803 |
NRSSILookupTable Control (G PHYs), also used for the TR Lookup Table |
0x804 |
NRSSILookupTable Data (G PHYs) |
0x80F |
LocalOscillator control register mask (G PHYs) |
0x810 |
LocalOscillator control register (G PHYs) |