ChipCommon

The ChipCommon core is a special core that does not exist in all chips and has a Core ID of 0x800. If present, the ChipCommon core is always the first core, at core index 0.

These are the relevant chipcommon registers, these can be accessed at their respective addresses after changing the current core to 0. Each register is a uint32.

Offset	Name	Usage
General
0x00	Chip ID	Explained Below
0x04	Capabilities	This is a bitfield and is explained below
0x08	Core Control	Only present if the Core Revision is >= 1
0x0C	bist	Unknown?
OTP Only present if Core Revision >= 10
0x10	OTP Status
0x14	OTP Control
0x18	OTP Prog
Interrupt Control
0x20	Interrupt Status
0x24	Interrupt Mask
0x28	Chip Control	Revision >= 11 Only
0x2C	Chip Status	Revision >= 11 Only
JTAG Master Only present if Core Revision >= 10
0x30	JTAG Command
0x34	JTAG IR
0x38	JTAG DR
0x3C	JTAG Control
Serial Flash Interface
0x40	Flash Control	Serial Flash Interface Control Register
0x44	Flash Address	Serial Flash Interface Addressing Register
0x48	Flash Data	Serial Flash Interface Data Register
Silicon Backplane Configuration Broadcast Control
0x50	Broadcast Address
0x54	Broadcast Data
GPIO Registers Cleared only by power on reset
0x60	GPIOIN	GPIO Input
0x64	GPIOOUT	GPIO Output
0x68	GPIOOUTEN	GPIO Output Enable
0x6C	GPIO Control	GPIO Control
0x70	GPIO Polarity	GPIO Pin Polarity
0x74	GPIO Interrupt Mask	GPIO Interrupt Mask
Watchdog Timer
0x80	Watchdog Timer
Clock Control Registers
0x90	Clock Control N
0x94	Clock Control SB	(M0)
0x98	Clock Control PCI	(M1)
0x9C	Clock Control M2	(M2/uart/mem)
0xA0	Clock Control MIPS	(M3)
0xA4	UART Clock Divider	Only present if Core Revision is >= 3
PLL Delay Registers Only present if Core Revision is >= 4
0xB0	pll_on_delay
0xB4	fref_sel_delay
0xB8	slow_clk_ctl	Only Present if Core Revision is between 6 and 9 inclusive
Instaclock Registers Only if Core Revision is >= 10
0xC0	System Clock Control
0xC4	Clock State Stretch
External Bus Control Registers Only if Core Revision >= 3
0x100	PCMCIA Config
0x104	PCMCIA Mem Wait
0x108	PCMCIA Attr Wait
0x10C	PCMCIA IO Wait
0x110	IDE Config
0x114	IDE Mem Wait
0x118	IDE Attr Wait
0x11C	IDE IO Wait
0x120	Prog Config
0x124	Prog Wait Count
0x128	Flash Config
0x12C	Flash Wait Count
UART 1
0x300	Data
0x304	IMR
0x308	FCR
0x30C	LCR
0x310	MCR
0x314	LSR
0x318	MSR
0x31C	Scratch
UART 2
0x400	Data
0x404	IMR
0x408	FCR
0x40C	LCR
0x410	MCR
0x414	LSR
0x418	MSR
0x41C	Scratch

$/!\$ At 0xF00, the normal core information registers are present

Chip ID

Mask	Usage
0x0000FFFF	Chip ID
0x000F0000	Chip Revision
0x00F00000	Package Options
0x0F000000	Number of Cores (Core Revision >= 4)

Capabilities Field

Mask	Usage
0x00000003	# of UARTs
0x00000004	MIPS in Big Endian Mode
0x00000018	UART Clock Select
0x00000020	UARTs on GPIO 15-12
0x000000C0	External Buses Present
0x00000700	Flash Type
0x00038000	Type of PLL
0x00040000	Power Control
0x00380000	OTP Size
0x00400000	JTAG Master Present
0x00800000	Internal Boot Rom Active
0x08000000	64 Bit Backplane