bcm-specs

[Specification

This page describes how the chipset is accessed through the backplane.

Backplane Function

The backplane functions almost like a MMU where it is possible to map certain locations (cores it contains) into the exported memory.

PCI Configuration Registers

Offset

Size

Usage

0x80

4

Backplane Address Space 0 mapped into mapped memory (CBAE)

0x84

4

Backplane Address Space 1 mapped into mapped memory

0x88

4

SPROM Control

0x8C

4

Backplane Address 1 Burst control

0x90

4

PCI Interrupts

0x94

4

PCI Interrupt Control Register/Interrupt Mask (PCI Revision 6 or greater only)

0x98

4

Backplane Interrupts

0xB0

4

PCI Configuration Space GPIO Input (PCI Revision 3 or greater only)

0xB4

4

PCI Configuration Space GPIO Output (PCI Revision 3 or greater only)

0xB8

4

PCI Configuration Space GPIO Output Enable/Disable (PCI Revision 3 or greater only)

CBAE

This register controls which backplane address is currently mapped into the mapped memory. Valid entries are 0x18000000 + Core Index * 0x1000, where Core Index is the Index of the core you want to map. Note that mapping may not succeed on the first attempt, so the proper method of mapping is to write the register, then read back the value until it is actually set to the desired value. To find which core is mapped, read this register and do the above calculation in reverse.

PCI GPIO Registers

See PowerControl

Other Registers

PCI_REVISION_ID
The Chip Revision
PCI_SUBSYSTEM_VENDOR_ID
The Board Vendor
PCI_SUBSYSTEM_ID
The Board_Type
PCI_STATUS
The PCI_STATUS_SIG_TARGET_ABORT bit is used.

PCI Mapped Memory

0x0000 - 0x0FFF

This is the area where the backplane address (of a core) is mapped into the PCI memory visible to the host processor.

The last 256 bytes (0xF00-0xFFF) of this area contain the core information registers for each core.

0x1000 - 0x1FFF

Of this space, only 0x1000-0x107F is used as the SPROM, the rest is unused as far as I can tell.

Finding the Chip ID

Use the CHIPID field of the ChipCommon core and'ed with 0x0000ffff, if no ChipCommon core is present then use the following table:

PCI device ID

Chip ID

0x4710 .. 0x4715

0x4710

0x4610 .. 0x4615

0x4610

0x4402, 0x4403

0x4402

0x4305 .. 0x4307

0x4307

0x4301

0x4301

Finding the Chip Packaging Value

Use the CHIPID field of the ChipCommon core AND'd with 0x00F00000 then shifted right by 20. The meaning of the value is currently unknown.

Finding the Chip Revision

If a ChipCommon core is present, use it's chip revision. Otherwise, use the PCI_REVISION_ID PCI information field.

Finding the Number of I/O Cores

if the COREREV of the ChipCommon core is 4 or >= 6, the number of I/O cores is encoded as (CHIPID[of the ChipCommon core] & 0x0F000000) >> 24, otherwise (or if no ChipCommon core is present), use this table:

Chip ID

Number of I/O Cores

0x4710, 0x4610, 0x4704

9

0x4402

3

0x4307, 0x4301

5

0x4310

8

0x4306

6

0x5365

7

Attaching to the Chipset

  1. Powercontrol_set_crystal on (see PowerControl)

  2. Clear the PCI_STATUS_SIG_TARGET_ABORT bit in PCI_STATUS, I'll refer to this operation as clear-target-abort later.

Detaching from the Chipset

  1. Turn interrupts off (see Interrupts)

  2. Clock down to slow speed (see PowerControl) if the chip has a slowclock which is indicated by the bit 0x20 in BoardFlags.

  3. Turn crystal off (see PowerControl)

Enabling/Disabling I/O Cores

Resetting (and also Enabling) an I/O Core

There's an extra flags parameter you need for this (core specific flags)!

  1. Disable the core (pass the flags!)
  2. Set sbtmstatelow to 'force gate clock' | 'reset' | 'clock enable' | flags
  3. Wait for 1usec
  4. If the S Error bit in sbtmstatehigh is set, set sbtmstatehigh to 0
  5. If the inband error or timeout bit is set in sbtmstate, turn both off
  6. Set sbtmstatelow to 'force gate clock' | 'clock enable' | flags
  7. Wait for 1usec
  8. Set sbtmstatelow to 'clock enable' | flags
  9. Wait for 1usec

Disabling an I/O Core

Just like when enabling, you need an extra flags parameter (core specific flags).

  1. Do nothing if core is in reset, that is the 'reset' bit is set in sbtmstatelow
  2. If the clock is not enabled ('clock enable' bit is not set in sbtmstatelow) skip to the last step
  3. Set sbtmstatelow to 'reject' | 'clock enable'
  4. Wait until the 'reject' bit is set in sbtmstatelow
  5. Wait until the 'busy' bit in sbtmstatehigh is no longer set
  6. Set sbtmstatelow to 'force gate clock' | 'reject' | 'reset' | 'clock enable' | flags and wait for 10usecs
  7. Set sbtmstatelow to 'reset' | 'reject' | flags

Checking if an I/O Core is Enabled

This is almost trivial, you need to check if of the 'clock', 'reset' and 'reject' bits in sbtmstatelow exactly 'clock' is set, if so the core is up, otherwise it isn't.

Making an I/O Core Usable (Interrupts, etc.)

In order to use an I/O core, you need to enable it in the backplane so you can get interrupts.

When enabling /O cores, you need a bitmask of the cores you want to enable by index (so, to enable a core with index 0, the bitmask is just 1<<0).

  1. Get the backplane flag number (see core information registers) of this core

  2. Switch to PCI core
  3. If this is a PCI Core with revision 6 or greater or this is a PCI-E core
    1. Bitwise OR the ICR PCI space register (32 bits) with the core enable bitmask shifted left by 8
  4. Otherwise
    1. Turn on the bit 1 << backplane flag number in the sbintvec register

  5. If this is a PCI Core
    1. Enable prefetch and burst in the sbtopci2 register (don't clobber other settings!)
    2. If the PCI core revision is < 5

      1. Set the service timeout (in the sbimconfiglow register) to 2
      2. Set the request timeout to 3
      3. Commit these settings (as below)
    3. If the PCI core revision is >= 11

      1. Set bit 0x20 (Memory Read Multiple) in the sbtopci2 register
  6. Otherwise, if this is a PCI-E Core
    1. If the PCI-E Core Revision is 0 or 1
      1. Set bit 0x8 in the PCI-E register PCI-E TLP Workaround register
    2. If the PCI-E Core Revision is 0
      1. Write 0x8128 to the MDIO/SERDES RX Device, Timer Register
      2. Write 0x0100 to the MDIO/SERDES RX Device, CDR Register
      3. Write 0x1466 to the MDIO/SERDES RX Device, CDR BW Register
    3. If the PCI-E Core Revision is 1
      1. Set bit 0x40 in PCI-E register PCI-E DLLP Link control register
  7. Switch back to the previous core

Committing PCI Settings

  1. Turn off the interrupts
  2. If the ChipCommon Core exists

    1. Switch to the ChipCommon Core if needed

    2. Write the 0xFD8 to the Silicone Backplane Broadcast Address Register, then write 0 to the Silicone Backplane Broadcast Data Register this forces an update of the cached registers
  3. Otherwise, use the PCI core
    1. Switch to the PCI Core if needed
    2. Broadcast the value 0 to address 0xFD8, this forces an update of the cached registers (see pci core#broadcast)

  4. Switch back to the original core
  5. Restore interrupts

Exported/Archived from the wiki to HTML on 2016-10-27